The difficulty of testing digital integrated circuits is increasing at a rapid pace with the increasing complexity of digital design. This testing typically occurs at the time of a circuit's manufacture, at start-up of a system that includes a circuit, or periodically while the circuit is functioning. With the technology delving into deep sub-micron feature size, digital designs are placing multi-million transistors in a single integrated circuit. Along with the tremendous increase in number of devices, the operating frequency, or clock speed, is reaching into the Gigahertz (109) range. Access to devices within an IC for test, for example, has become a problem with the increase in device count. The ratio of pin to device is gradually decreasing, resulting in increasing cost of test generation. External testers are also becoming prohibitively expensive for testing multiple hundred Megahertz and Gigahertz frequency digital ICs.
Built-in self-test (BIST) has emerged as a viable alternative to expensive external testing. In general, BIST schemes are based on test stimulus supplied by a pseudo-random pattern generator (PRPG) residing within the IC itself. Responses to the test stimulus are collected in a response compactor within the IC and made available at the end of the test. Thus, the cost of access, test generation, and expensive tester hardware can be resolved by implementing BIST techniques to test digital ICs.
Although BIST provides an alternative to external test, the issue of the quality of the testing remains the same for both paradigms. The limitation of classical stuck-at fault based testing is well established in present day technology (CMOS, etc.) and deep sub-micron feature size. Shrinking feature size together with multiple layers of metal connections in semiconductor processes is resulting into new failure modes. AC failures are becoming equally important with static failures. Digital ICs today need to be tested for performance at Gigahertz operating frequencies to make sure that the devices can operate at without failure. At-speed testing based on delay fault model is becoming part and parcel of a high quality digital test. BIST schemes thus need to provide for at-speed testing to be effectively applicable to high speed digital ICs.
A basic infrastructure for built-in self-test of digital ICs is described in U.S. Pat. No. 4,503,537. The patent discloses a linear feedback shift register (LFSR) as the source of random patterns. A Multi Input Shift Register (MISR) is used as the unit to collect and compact test responses. Multiple parallel scan chains are connected between the LFSR and MISR for inserting test vectors into the circuit under test and capturing the results. A BIST controller coordinates the loading of scan chains with pseudorandom patterns from the generator. After the loading of a pseudorandom pattern is completed, a single capture clock is applied to capture the responses into the scan chains. Subsequently the responses are shifted out and compressed into a signature. In this method all scan chains are assumed to operate at the same frequency. If the circuit has multiple frequencies, it has to operate at the slowest frequency to allow enough time for signals in those slow domains to propagate reliably to steady states before they are captured. The transitions are generated by the last shift in every loading sequence. All responses are captured simultaneously. Also disclosed therein is the well-known scan technique wherein scan chains are implemented in a digital circuit design by dividing the design into combinational and sequential logic.
As taught in the patent and elsewhere in the literature, the sequential logic is used as scan cells that can be configured into scan chains during testing of the circuit. A typical scan cell contains a two-input multiplexer followed by a sequential or memory element such as a flip flop. The flip flop is an edge-triggered sequential element where input data is latched into the element at the active edge of the clock signal. The multiplexer control signal (known as scan enable, or SE) determines the mode of operation for the scan cells during test: scan or capture. In scan mode, the scan cells are connected in series to form a scan chain and the combinational logic is decoupled from the scan chain. Test stimulus in the form of a test vector of data is brought in from a source such as a PRPG and clocked into the scan chain. In capture mode, data is propagated from input scan cells through functional paths of the combinational logic and captured in output scan cells (which may be the same as or different from the input scan cells). Capture mode exercises the logic's functional paths and hence performs testing of the faults in these structures. After capture, the scan enable changes the cell operation back to scan mode and the captured data is shifted out into a response compactor such as a multiple input signature register (MISR). While the response is shifted out for one scan vector, input data is shifted in for the next scan vector. Shift in and shift out become parallel operations. After the last scan vector is shifted into the MISR, a signature is obtained in the MISR. This signature is compared with a fault-free signature to determine if the digital circuit is fault-free.
In BIST, therefore, there are two distinct operations during test: scan and capture. The scan operation shifts test data into a scan chain. Once there, the test data is available in the scan chain for propagation through the circuit. The capture operation then captures the test data response after the data has propagated through the circuit, normally within one clock cycle of the digital circuit's clock. The scan operation then shifts the response out of the scan chain
The quality of at-speed testing is determined by two edges of the functional clock. The clock edge at which the last shift occurs is the update edge. The update edge applies the test vector to the combinational logic. The capture edge is the clock edge at which the memory elements capture the test vector response. An alternative scheme uses the capture clock to provide both update and capture edges.
The minimum time between an update edge and a following capture edge is the time allowed for the data to propagate through the combinational logic. This time window is termed the “at-speed path.” FIGS. 1A and B illustrate the concept of an at-speed path. FF22 is the driving end flip flop and FF24 is the receiving end flip flop. In FIG. 1A, a last shift updates data into FF22 at the rising edge of the clock that provides the circuit's operating frequency. At the next rising edge of the clock, data is captured into FF24. Thus, one clock cycle is the at-speed path in the first case. In FIG. 1B, a last shift updates data into FF22 at the falling edge of the clock. At the next rising edge, data is captured into FF24. Thus, about one-half clock cycle is the at-speed path in the second case.
Testing of digital circuits is ideally done at the speed that the circuits are normally clocked (at-speed testing). As clock speeds have reached Gigahertz frequencies, this had led to problems with the scan operation data in BIST. First, shifting data through a scan chain results in simultaneous switching of large number of signals. At high clock speeds, this shifting and switching generates very high power and heat that can damage the circuit under test. Second, at-speed shifting often provides insufficient time for the scan enable control signal to change from a scan to capture state before the arrival of the capture edge of the clock.
In addition to problems with scan operations during at-speed testing, another challenge faced by BIST schemes is handling the multiple clock domains typically found in complex digital ICs. Each clock domain (which includes a scan chain and possibly other logic) has its own operating frequency. Interaction of these clock domains results in additional complexity in at-speed testing. Both under-testing (testing at slower than the normal operating frequency) and over-testing (testing at faster than the normal operating frequency) can affect the quality and yield of the IC.
The above definition of an at-speed path also applies in digital circuits that have multiple clock domains with multiple clock frequencies. FIG. 2 shows a typical digital circuit having three clock domains. Each clock domain has a scan chain (SC1, SC2, and SC3) and an operating frequency (F1, F2, and F3, respectively) provided by a clock (CLK1, CLK2, and CLK3, respectively). Frequency F1 is greater than F2, and F2 is greater than F3. The timing relationships for the various at-speed paths are shown in FIGS. 3A-E. Assuming all the scan elements in these scan chains are rising edge flip flops, the definition of at-speed test for intra-clock domains are shown in FIG. 3B. For example in clock domain CLK1, at-speed path p11 is between two consecutive rising edges of CLK1. The driving end flip flop F22 updates data on rising edge t1 and receiving end flip flop F24 captures data on the next rising edge t2. Inter-clock domain at-speed paths are shown in FIGS. 3C-E. For example, path p12 in FIG. 3C is an at-speed path between CLK1 and CLK2, beginning at rising edge t2 on CLK1 and ending at rising edge t3 on CLK2. Path p12′, however, is not an at-speed path because there is an intervening update edge t2 update edge t1 and capture edge t3. Similarly in, p21 in FIG. 3C is an at-speed path between CLK2 and CLK1, P31 and p13 in FIG. 3D are at-speed paths between CLK 1 and CLK3, and p32 and p23 in FIG. 3E are at-speed paths between CLK 2 and CLK 3.
Method and apparatus for testing digital circuits with multiple clock domains are known, but each has significant drawbacks. U.S. Pat. No. 5,680,543, for example, discloses testing the multiple clock domains sequentially rather than in parallel, which lengthens the test. Moreover, inter-domain testing (where two clocks affect combinational logic through which the test data is propagated) is not done at speed, providing flawed results. Another limitation of the described scheme is a limited ability to deal with clock skews (the inability to simultaneously clock a circuit with clocks from two domains). Similarly, U.S. Pat. No. 5,349,587 advocates simultaneous capture in multiple clock domains, which makes this scheme sensitive to clock skew between domains. Furthermore, inter-domain testing is not done at speed. Moreover, the scan enable signal changes during the active edge of the clock, which may create a highly undesirable race condition.
An objective of the invention, therefore, is to provide a method and apparatus for providing accurate, at-speed testing of digital circuits that may have multiple clock domains.